AbstractWhether or not a Proportional + Integral + Derivative (PID) controller is suitable for stabilising power supplies has become an emotive debate rather than a scientific discussion. The debate has been compounded by the arrival of many digital power solutions, which seem to come as standard with a PID controller programmed in their software. People like PID controllers for their simplicity and are reluctant to change what they know and love for something else that performs better, but needs a more detailed understanding of control theory. In this article we would like to present our reasons as to why, here at Biricha we try to avoid using PID controllers for the majority of the power supplies that we design. This is merely our opinion and is not intended to restart a debate, and as such, we ask you to decide for yourselves as to whether or not PID is suitable for your application. IntroductionPID controllers are extremely easy to design and implement. With less than 10 minutes on any search engine you will find many analog and digital realizations; there are even automatic tuning algorithms. Whilst this controller and its close relative (PI) are excellent for stabilizing motor control systems or temperature controllers and the like, it is our opinion that they are unsuitable for compensating most switch mode power supplies. Furthermore, although one may be able to get away with using a PID controller in a current mode converter, there are better alternatives. If you do intend to use a PID controller, we highly recommend reading the excellent analysis by Christophe Basso which was presented at APEC in 2011 and is available for free on Mr Basso’s website [1]. The main attraction of PID is that one does not need to know much about control theory, frequency response analysis, polezero placement, phase margin, gain margin, stability criteria, etc etc. Instead, you heuristically (i.e. scientific word for semieducated trial and error) change the compensator’s 3 gain terms to achieve the desired response. Though this method is extremely effective in millions of applications, we feel that it is not suitable for power supply design. Most experts agree that switching power supplies should be designed in the frequency domain, and yet PID is a tool whose main advantage is that you don’t design in the frequency domain! This is a contradiction and, therefore, you can see from the onset that PID is not suitable for what we are trying to do, even though it is ideal for many other applications. PID Compensator ExplainedThe transfer function of the PID is shown in Equation 1 Please register or login to download the complete version of this resource Equation 1 Where, Kp is the proportional gain, Ki is the integral gain, Kd is the differential gain and s is the Laplace operator. The design procedure is usually based around simply changing these gains until our control system’s transient response becomes satisfactory after a unit step. Please note that we are now working in time domain and not frequency domain. However, almost everyone agrees that we should design our power supplies in frequency domain to ascertain a measure of our relative stability. So, how does changing these gains heuristically impact our poles and zeros in frequency domain? How do we assess that we do not violate the stability criteria? Let us find out! If we take common denominators on the previous equation, we will have: Please register or login to download the complete version of this resource Equation 2 You can immediately see that the numerator is a simple quadratic equation i.e. we have 2 zeros and in the denominator we have only 1 pole, which is at the origin. Please note that for a realizable system we need another pole, but this will have to be placed so high in frequency that it does not impact the transfer function at the frequencies of interest (or it would not be a pure PID ) To find the zeros, we need to solve the quadratic using: Please register or login to download the complete version of this resource Equation 3 In our case a = Kd, b = Kp and c = Ki; substituting these in the above equation we have: Please register or login to download the complete version of this resource Equation 2 Looking at the equation above you will see that the positions of both zeros and the pole at origin are interdependant on all three gains. This means that if you change any of the gains you will mess up the position of everything in frequency domain! If you wish to place your pole and zeros intelligently, then you will have to derive the modulus and the phase of the transfer function, then solve several equations simultaneously and place the 2 zeros and the only pole in such a way so as to meet the stability criteria (please see our previous articles about loop stability). Hang on, I hear you say; wasn’t the whole point of PID that we did not have to do this sort of analysis? The answer is yes, but we have to do this to show why it will not work very well! If you are already convinced, then please stop reading the rest of this article and pick up one of the many fantastic books in this field, written by experts and design a proper Type III compensator. There are several excellent book on the market (e.g. Basso, Erickson & Maksimovic), but for an eloquently written section on loop stability, and simple explanation of control loops, I really like Mr Maniktala’s Red A to Z book [2]. So Why Will Our PID Not Work Very Well?Voltage Mode PSU performance with a Type III compensatorFrom the following figure you can see an optimally compensated voltage mode power supply with a Type III compensator using our WDS software [3]. You can see that we have got a good crossover, phase margin and gain margin. We have also marked danger zones you should try and avoid crossing at. Please register or login to download the complete version of this resource Figure 1. Loop Bode plot of voltage mode Buck plant + Type III compensator For this power supply, we have kept the default values so that you can use our evaluation version to reproduce these experiments exactly. Please just download a free copy from our website (www.biricha.com/wds) and you can repeat these experiments yourselves. WDS also allows you to run a spice simulation using LTSpice and the following figure is the result of a 50% step load. You can see that our Type III compensator is performing very well. Please register or login to download the complete version of this resource Figure 2. Transient response test for Type III compensator designed using WDS Voltage Mode PSU performance with a PID compensatorNow let us see if we can design a PID compensator in WDS with a similar performance. In order to do this, all you have to do is to select a Type III and then manually set the two poles (not the pole at the origin) to 10MHz so that they do not impact the control loop. You now have a PID controller. With a PID, we only have 2 zeros and one pole at the origin. In order to meet the stability criteria, we must place our zeros at around the resonance frequency, otherwise we will cross with a sharp slope. We can then use the pole at origin to get a high gain at low frequencies and a good cross over. (Please see our previous articles on this subject). So if we cancel the 2 plant poles with our 2 PID zeros and then place our PID’s pole at the origin, the gain of our open loop frequency response will be rolling off at a rate of 20 dB/decade. We will then hit our capacitor’s ESR zero. If our gain is going down at 20dB/decade and then hits a zero, then the gain plot will go flat with a gradient of 0dB/decade. There are only 2 options: either it will go flat before we cross over, i.e. we don’t cross at all, or it will go flat after we cross over i.e. we may end up with very little gain margin. The best way to get a good feel of this is to simulate. You can simply download the evaluation version of WDS and keep all the default values. In the “Controller Design” tab under “Controller Poles and Zeros” select “Manual Placement” then set the two zeros at the resonant frequency (~1.7kHz), set “First Pole” and “Second Pole” to 10MHz to minimize their impact and then experiment with the “Pole at the Origin”, you will see how hard it is to cross at a reasonable position without violating the stability criteria. You can then run an LT Spice simulation from within WDS from the Spice Simulation Tab. Let us first see what happens if the loop does not cross: The figure below shows the loop response with our PID’s pole and zeros placed in such a way that the loop goes flat before we cross the 0dB axis. Please note that Bode’s stability terms such as gain margin and phase margin are only defined at crossover frequency. If we do not cross, then we have absolutely no idea of whether this power supply is stable or not. We can either resort to looking at the Nyquist plot (even more analysis) or make sure that we do cross. Please register or login to download the complete version of this resource Figure 3. Loop Bode plot of voltage mode Buck plant + PID compensator which does not have a crossover frequency. Now let us look at Spice simulation of the above PSU’s output ripple voltage: Please register or login to download the complete version of this resource Figure 4. Output ripple with a PID that does not have a crossover frequency. The above does not even take into consideration that we don’t have Kp, Ki and Kd’s relationships with the positions of our pole and zeros and that they are interdependant! How are we going to make this power supply stable “heuristically” by playing with these values? The short answer is that we can’t without a great deal of mathematical analysis in frequency domain! Fortunately WDS will do this for you, but we have lost the main advantage of PID’s which was its ease of design in time domain. Now what if we do cross? Can we get a better performance? The answer is no. In the following figure we changed the position of the pole at the origin in WDS to make sure that the loop does cross at 20kHz just like our Type III. But please have a look at our gain; from our crossover up to half the switching frequency (Fs) we are only 2dBs below the 0dB point! This may work in this simulation, but in real life the loop may cross the 0dB point many times! This is very dangerous; it is certainly not a product you can ship! Again, we recommend having a play with WDS yourself to see if you can get a good response. Please register or login to download the complete version of this resource Figure 5. Loop Bode plot of voltage mode Buck plant + PID compensator which has an unknown gain margin. Current Mode PSU with PID ControllersIt is certainly possible to stabilize a current mode PSU with a PID controller. After all, at low frequencies our plant’s transfer function “looks” like a first order system and we usually use a Type II compensator which ONLY has one zero, one pole at origin and extra pole. So our PID only has one pole less than a Type II. The Type II’s extra pole is usually used to cancel the capacitor’s ESR zero; so with this pole missing again our loop will go flat at some point. However, if we derived the mathematical relationships between Kp, Ki, Kd and our pole and zeros then by clever pole zero placement, we could possibly get a relatively stable power supply. The question is, if we need to do all these derivations, why not just use a Type II? PID and Digital ControllersThe use of PID has been suggested by almost all digital power supply IC vendors. The irony of course is that digital power supplies are by far more susceptible to instability when used with a PID than analog ones [4]. The reason is that the phase in a digital power supply deteriorates much faster than an analog equivalent. This extra phase erosion is due to the sampling and reconstruction on our discrete time system. The net result is that our phase usually crosses the 180 degree point and therefore we must have at least 10 dB of gain margin. However, with the loop flattening, the gain margin will be poor. In the following figure we have used WDS to design a digital power supply with similar specification to the analog ones (again you can try these yourselves with our evaluation version). Please register or login to download the complete version of this resource Figure 6. Bode plot showing phase erosion in a digital power supply. You can easily see how much faster the phase is rolling off compared to an analog supply. Furthermore, as it crosses the 180 degree point our gain margin is very poor indeed. The spice simulation of the step response for this power supply is shown in the following figure. Note that even though we have 70 degrees of phase margin, due to the low gain margin, we still have large undershoot and ringing. We must stress at this juncture that, this is only a simulation and a digital power supply in real life, with this specification, will almost certainly be completely unstable for many different reasons. Please register or login to download the complete version of this resource Figure 7. Transient response of equivalent, incorrectly designed, digital power supply Concluding RemarksIn this article, we discussed why we feel that a PID controller is not best suited for stabilising most switch mode power supplies. We supported our hypothesis with transfer function analysis, and various simulations in both frequency and time domain. We believe that switch mode power supplies are best designed in frequency domain and presented the main downfall of PID as the need to heuristically adjust the gain terms in time domain. Things to Try1 – Download a copy of Biricha WDS PSU Design software 2 – Attend one of our Analog Power Supply Design workshops Bibliography[1] "The Dark Side of Loop Control Theory" by C. Basso, APEC 21011 [2] “Switching Power Supplies A  Z, Second Edition 2nd Edition” by Sanjay Maniktala [3] Biricha Digital’s “Analog PSU Design Workshop” Handbook Comments are closed.
